1. Field of the Invention
The invention relates in general to the fabrication of a dynamic random access memory (DRAM), and more particular to the fabrication of a DRAM capacitor with a larger surface area to increase its cell capacitance.
2. Description of the Related Art
A single DRAM cell includes a metal oxide semiconductor (MOS) transistor and a capacitor. The capacitor is the heart area for storing signals. If the capacitor stores larger amount of charges, the influence of noise as data writing and reading becomes less and also the frequency of refresh decreases. Methods for increasing the charge storage ability of the capacitor includes: (1) increasing the surface area of the capacitor to increase the number of charges stored in the capacitor; (2) selecting proper dielectric material with high dielectric constance to increase the number of stored charges per area; and (3) reducing the thickness of the dielectric layer but the technique of fabricating a thin dielectric layer is rather limited.
Referring to FIG. 1, showing a circuit diagram of a DRAM cell, a memory cell is composed of a MOS transistor T and a storage capacitor C. Source region of the MOS transistor T is coupled to a corresponding bit line BL, drain region of it is coupled to a storage electrode 15 of the storage capacitor C, gate region of it is coupled to a corresponding word line WL. An opposed electrode 14 of the storage capacitor C is coupled to a fixed voltage source. A dielectric layer 1 2 is deposited between the storage electrode 15 and the opposed electrode 14.
Conventionally, hemispherical grain polysilicon (HSG) is frequently utilized for the fabricating of a lower electrode of a DRAM capacitor to increase the surface area of a electrode plate. Referring to FIGS. 2A to 2E, these figures illustrate the fabrication method of a conventional DRAM. Referring first to FIG. 2A, the MOS device and the silicon substrate 20 under the insulating layer 22 are only partially illustrated. The insulating layer 22, such as an inter-polysilicon dielectric layer (IPD) 22, can be used to isolate from other devices. There is a via at the IPD layer 22, exposing the source/drain regions (not shown) of the MOS device. A conductive material 24, such as doped polysilicon, is then used to fill the via and cover the IPD layer 22.
Referring to FIG. 2B, on the surface of the conductive layer 24, a HSG layer 26 is formed by plasma enhanced chemical vapor deposition (PECVD), using tetra-ethylortho-silicate (TEOS) as gas source. Next, the HSG layer 26 is doped with impurities by ion implantation to increase its conductivity. Due to the formation of a native oxide layer on the surface of the HSG layer 26, during the process of forming the HSG layer 26, the quality of the capacitor is seriously influenced. Therefore, the chip is dipped in etchant such as RCA-HF to remove the native oxide layer on the surface of the HSG layer 26, wherein the RCA etchant includes NH.sub.4 OH, hot deionized water (HDIW) and H.sub.2 O.sub.2.
Referring to FIG. 2C, a photoresist layer 28 is formed on the HSG layer 26 to define a lower electrode.
Referring next to FIG. 2D, the HSG layer 26 and the conductive layer 24 are etched, using the photoresist layer 28 as a mask. After the removal of the photoresist layer 28, the patterned conductive layer 24 and HSG layer 26 together form the lower electrode 25 of the capacitor.
Referring to FIG. 2E, a dielectric layer 32 is deposited to cover the lower electrode 25. The dielectric layer 32 can be a triple layer structure such as a silicon oxide/silicon nitride/silicon oxide layer, a double layer structure such as a silicon nitirde/silicon oxide layer or Ta.sub.2 O.sub.5. Finally, an upper electrode 34 is deposited.
A conventional lower electrode with a top-HSG layer has a cell capacitance for about only 1.7 times larger than a lower electrode without a top-HSG layer.